研究方向
1. 新型低功耗逻辑与存储器件
2. 神经形态器件及集成技术
3. 器件可靠性及波动性研究
代表性科研论文
1. Q. Huang, R. Jia, J. Zhu, Z. Lv, J. Wang, C. Chen, Y. Zhao, R. Wang, W. Bu, W. Wang, J. Kang, K. Hua, H. Wu, S. Yu, Y. Wang, and R. Huang, Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization. International Electron Devices Meeting (IEDM), session 31.5 , Dec. 2016.
2. X. Jiang, S. Guo, R. Wang, Y. Wang, X. Wang, B. Cheng, A. Asenov, and R. Huang, New insights into the near-threshold design in nanoscale FinFET technology for sub-0.2V applications. International Electron Devices Meeting (IEDM), session 28.4, Dec. 2016.
3. Z. Zhang, Z. Zhang, R. Wang, X. Jiang, S. Guo, Y. Wang, X. Wang, B. Cheng, A. Asenov, and R. Huang, New Approach for Understanding "Random Device Physics" from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results. International Electron Devices Meeting (IEDM), session 7.2, 2016.
4. Z. Wang, M. Yin, T. Zhang, Y. Cai, Y. Wang, Y. Yang and R. Huang, Engineering incremental resistive switching in TaOx based memristors for brain inspired computing. Nanoscale, 8,14015-14022, 2016.
5. X. Yang, Y. Fang, Z. Yu, Z. Wang, T. Zhang, M. Yin, Y. Yang, Y. Cai and R. Huang, Nonassociative learning implementation by a single memristor-based multi-terminal synaptic device. Nanoscale, DOI: 10.1039/C6NR04142F, 2016.
6. Q. Huang, R. Jia, C. Chen, H. Zhu, L. Guo, J. Wang, J. Wang, C. Wu, R. Wang, W. Bu, J. Kang, W. Wang, H. Wu, S.-W. Lee, Y. Wang, and R. Huang, First Foundry Platform of Complementary Tunnel-FETs in CMOS Baseline Technology for Ultralow-Power IoT Applications: Manufacturability, Variability and Technology Roadmap. IEDM Technical Digest, 604-607, 2015.
7. X. Jiang, X. Wang, R. Wang, B. Cheng, A. Asenov, and R. Huang, Predictive Compact Modeling of Random Variations in FinFET Technology for 16/14nm Node and Beyond. IEDM Technical Digest, 727-730, 2015.
8. P. Ren, X. Xu, P. Hao, J. Wang, R. Wang, M. Li, J. Wang, W. Bu, J. Wu, W. Wong, S. Yu, H. Wu, S.-W. Lee, D.Z. Pan, and R. Huang, Adding the Missing Time-Dependent Layout Dependency into Device-Circuit-Layout Co-Optimization--New Findings on the Layout Dependent Aging Effects. IEDM Technical Digest, 293-296, 2015.
